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DA9188.002 23 February 2005
MAS9188
12 x 8-Bit D to A Converter
3-Pin Serial Data Interface Low Voltage Output Buffer Replaces 12 Potentiometers Individually Programmable Outputs * Fully Operational Down to 1.2 V * * * *
DESCRIPTION
MAS9188 is 12-channel 8-bit DAC, designed primarily for trimmer replacement. The device is controlled by a simple 3-line input. The DAC is selected with the four first bits in the serial input data (SDI-pin) and the DAC output value is set according to the last 8 bits in the serial input data.
FEATURES
* * * * * * Twelve 8-Bit DACs on a Single Monolithic Chip Voltage Level Output TSSOP-20 Package Single, Low +1.2 V Supply Power-On Reset Functionally and Pin Compatible with AD8802/AD8804
APPLICATIONS
* * * * High Resolution Monitors Automatic Gain Control Trimmer Replacement Portable and Battery-Operated Equipment
BLOCK DIAGRAM
SDI CLK
12-bit Shift Register
8-bit data
8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC
O12 O11 O10 O9 O8 O7
XCS
Address Decoder
8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC
O6 O5 O4 O3 O2 O1
VREFHVREFL
VDD
GND
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DA9188.002 23 February 2005
PIN CONFIGURATION
VREFH O1 O2 O3 O4 O5 O6 XSHDN XCS GND
1 2 3 4 20 19 18 17
VDD XRESET O12 O11 O10 O9 O8 O7 SDI CLK
VREFH O1 O2 O3 O4 O5 O6 XSHDN XCS GND
1 2 3 4
20 19 18 17
VDD O12 O11 O10 O9 O8 O7 SDI CLK VREFL
MAS9188A1 YYWW
MAS9188A2 YYWW
5 6 7 8 9 10
16 15 14 13 12 11
5 6 7 8 9 10
16 15 14 13 12 11
Top view YYWW = year, week
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MAS9188 A1 VREFH O1 O2 O3 O4 O5 O6 XSHDN XCS GND CLK SDI O7 O8 O9 O10 O11 O12 XRESET VDD MAS9188 A2 VREFH O1 O2 O3 O4 O5 O6 XSHDN XCS GND VREFL CLK SDI O7 O8 O9 O10 O11 O12 VDD Function DAC output reference high voltage DAC 1, address 0x0 DAC 2, address 0x1 DAC 3, address 0x2 DAC 4, address 0x3 DAC 5, address 0x4 DAC 6, address 0x5 Device analog part power-down signal (active low) Device enable signal (rising edge loads data to DAC) Device ground-pin Data clock / DAC output low reference voltage Serial input data / Data clock DAC 7, address 0x6 / Serial input data DAC 8, address 0x7 / DAC 7, address 0x6 DAC 9, address 0x8 / DAC 8, address 0x7 DAC 10, address 0x9 / DAC 9, address 0x8 DAC 11, address 0xA / DAC 10, address 0x9 DAC 12, address 0xB / DAC 11, address 0xA Device Digital part reset - middle code preset pin / DAC 12, address 0xB Device power supply pin
MAS9188 has two bonding options available:
* *
MAS9188A1, where VREFL pin is bonded to GND pin and XRESET pin can be used MAS9188A2, where XRESET pin is bonded to VDD pin and VREFL pin can be used
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DA9188.002 23 February 2005
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply (VDD to GND) Input Voltage Range (any other pin) Operating Temperature Range Storage Temperature Range Symbol VDD Conditions Min -0.3 -0.3 -40 -65 Max 6.0 VDD + 0.3 +85 +150 Unit V V C C
RECOMMENDED OPERATION CONDITIONS
Parameter Supply Voltage Range Operating Temperature Range Symbol VDD Temp Conditions Min 1.2 -40 Typ 3.6 Max 5.5 +85 Unit V C
ELECTRICAL CHARACTERISTICS
DC Parameters Digital Inputs Parameter DAC Resolution DAC Differential Nonlinearity Error DAC Integral Nonlinearity Error DAC Full-scale Error DAC Zero Code Error DAC Output Resistance Reference Input Parameter REFH Voltage Range REFL Voltage Range (MAS9188A2 only) REFH Input Resistance REFL Input Resistance ROUT Matching (ROUT/ROUT)
VDD = 2.4...5.5 V, VREFH = VDD, VREFL = 0 V, -40C TA +85C unless otherwise noted
Symbol N DNL INL GFSE BZSE ROUT
Conditions
Min -1 -1 -1 -1 3
Typ 8
Max +1 +1 +1 +1
Unit Bits LSB LSB LSB LSB k
5
8
VDD = 2.4...5.5 V, VREFH = VDD, VREFL = 0 V, -40C TA +85C unless otherwise noted
Symbol VREFH VREFL RREFH RREFL RMATCH
Conditions VREFH > VREFL VREFH > VREFL
Min 0 0 0.5
Typ
Max VDD VDD
Unit
1.1 1.1 0.4 2
k k %
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DA9188.002 23 February 2005 Digital Input Parameter Digital Logic High Digital Logic Low Digital Input Current Power Supplies Parameter Power Supply Range Supply Current Shutdown Current
VDD = 2.4...5.5 V, VREFH = VDD, VREFL = 0 V, -40C TA +85C unless otherwise noted
Symbol VIH VIL IIL
Conditions
Min 0.7 x VDD
Typ
Max 0.3 x VDD 1
Unit
A
VDD = 2.4...5.5 V, VREFH = VDD, VREFL = 0 V, -40C TA +85C unless otherwise noted
Symbol VDD IDD ISHDN
Conditions
Min 1.2
Typ 0.01 0.01
Max 5.5 5 5
Unit V A A
AC Parameters AC Characteristics Dynamic Performance
VDD = 2.4...5.5 V, VREFH = VDD, VREFL = 0 V, -40C TA +85C unless otherwise noted
Parameter Power Supply Sensitivity Power Supply Sensitivity (100 Hz) Vout Settling time (1/2 LSB error band) Crosstalk between adjacent outputs Switching Characteristics
Symbol VOUT VDD PSRR TS CT
Conditions VDD = 1.1 x VDD - 0.9 x VDD
Min
Typ 0.12 65 5 50
Max
Unit % dB s dB
VDD = 3.6 V, VREFH = VDD, VREFL = 0 V, TA = +25C unless otherwise noted
Parameter Input Clock High Pulse Width Input Clock Low Pulse Width Data Setup Time Data Hold Time XCS Fall to First Clock Pulse Fall XCS High Pulse Width CLK Rise to XCS Rise Hold Time XCS Rise to CLOCK Rise Setup RESET Pulse Width
Symbol TCH TCL TDS TDH TCLCL TCSW TCSH TCS1 TRS
Conditions
Min
Typ 17 8 -7 24 18 10 22 7 18
Max
Unit ns ns ns ns ns ns ns ns ns
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DA9188.002 23 February 2005
OPERATING MODES
DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL) (note: VREFL = GND in case of MAS9188A1). The XRESET pin is used for middle code preset: DAC registers are reset and middle code will appear at the DAC output. Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register. Rising XCS-pin reads data and 12 CLK-cycles are used as the input data (4 address bits and 8 data bits). The last 12 bits before rising XCS are used as input data. Timing diagram
SDI
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK XCS VOUT
APPLICATION AND TEST CIRCUIT INFORMATION
+3.0v
DAC Register Load
20 VDD
1 VREFH
Power On/Off
MAS9188A2
8 XSHDN O12 O11 CLK SDI XCS O10 O9 O8 9 O7 O6 O5 O4 O3 19 18 17 16 15 14 7 6 5 4 3 2
Controller
Clock Data In Chip Select
12 13
100 nF
GND 10
O2 O1 VREFL 11
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DA9188.002 23 February 2005
PACKAGE (TSSOP-20) OUTLINES
e/ 2 A VIEW B-B b
E
E1
c1
c
12 REF S
b1 INDEX AREA GAUGE PLANE e
R
A
0.25 12 REF D L1
L
A
A2
b
B B b VIEW A-A
A1
Symbol A A1 A2 b b1 c c1 D E E1 e L L1 R S
Min -0.05 0.85 0.19 0.19 0.09 0.09 6.40 4.30 0.50 0.09 --
Nom --0.90 -0.22 --6.50 6.4 BSC 4.40 0.65 BSC 0.60 1.00 REF -0.20
Max 1.10 0.15 0.95 0.30 0.25 0.20 0.16 6.60 4.50 0.75 ---
Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm
Dimensions do not include mold or interlead flash, protrusions or gate burrs. Reference Standard : JEDEC MO-153 .
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DA9188.002 23 February 2005
SOLDERING INFORMATION
For For Eutectic Sn/Pb TSSOP-20 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 2*220C 240C 3 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 m, material Sn 85% Pb 15%
For Green (Pb Free, RoHS Compliant) TSSOP-20 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 260C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 m, material Matte Tin
EMBOSSED TAPE SPECIFICATIONS
PO
P2
P1
DO
X E
W
F
AO
User Direction of Feed
X T
Section X-X
Pin1
BO
KO
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DA9188.002 23 February 2005 Dimension Ao Bo Do E F Ko Po P1 P2 T W Min/Max 6.70 0.10 6.90 0.10 1.50 +0.1/-0.0 1.75 7.50 0.10 1.30 0.10 4.0 12.0 0.10 2.0 0.05 0.3 0.05 16.00 +0.30/-0.10 Unit mm mm mm mm mm mm mm mm mm mm mm
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DA9188.002 23 February 2005
REEL SPECIFICATIONS
W3
W2
A
D
C
N
W1 B
* * * *
2500 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative
Carrier Tape Cover Tape
End
Start
Trailer
Components
Leader
Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader
Min 1.5 12.80 20.2 50 16.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape
Max 330 13.50 18.4 22.4
Unit mm mm mm mm mm mm mm mm mm
Weight
1500
g
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DA9188.002 23 February 2005
ORDERING INFORMATION
Product Code MAS9188AUA1 MAS9188AUA2 MAS9188A1UC06 MAS9188A2UC06 Product 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter Package TSSOP-20 TSSOP-20 TSSOP-20 Pb free, RoHS compliant TSSOP-20 Pb free, RoHS compliant Comments 0 V Reference Level Adjustable Reference Level 0 V Reference Level Adjustable Reference Level
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
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